(a) Field of the Invention
The present invention relates to an embedded LSI and, more particularly, to an embedded LSI having a FeRAM section and a logic circuit section.
(b) Description of the Related Art
Recently, IC cards each having a nonvolatile memory device and a logic circuit embedded on a single substrate are expected to replace conventional magnetic cards. The nonvolatile memory device in the IC card generally includes a memory cell array and an associated peripheral circuit including a drive section and a decoder section, whereas the logic circuit includes a processing section for conducting data processing and an input/output section for conducting input/output processing in association with the peripheral circuit and the memory cell array.
With the increase in the amount of data to be stored in the memory cell array, a conventional EEPROM used as the nonvolatile memory device will be rapidly replaced by a FeRAM which has a larger storage capacity with high speed operation and low power disspation. The FeRAM has in each memory cell a ferroelectric capacitor having a ferroelectric film as a capacitor insulator film.
In fabrication of MOSFETs which constitute the logic circuit section in the embedded LSI, a hydrogen-annealing step is conducted to the wafer for several tens of minutes at a temperature of about 400 to 450xc2x0 C. in a hydrogen ambient containing several percents to fifty percents hydrogen. The hydrogen annealing step is conducted for the purpose of finally adjusting the transistor characteristics such as the interface state of the gate oxide, fixed electric charge, ON-current and threshold voltage of the MOSFETs. The hydrogen-annealing step is generally conducted after fabrication of the metallic interconnect structure and before formation of the passivation film.
In the FeRAM section in the embedded LSI, it is known that the ferroelectric capacitor having a ferroelectric film including a perovskite metal oxide such as PZT or BST is liable to desorption of oxygen from the ferroelectric film in a reducing ambient of the hydrogen-annealing. The desorption of oxygen damages the ferroelectric film of the ferroelectric capacitor and thus degrades characteristics of the ferroelectric capacitor, which is undesirable.
It is known that the desorption of oxygen is also incurred by a CVD process for depositing a metallic film in the interconnect structure or a plasma-enhanced CVD process for depositing a silicon oxide film as an interlayer dielectric film. This is because these CVD steps also generate hydrogen similarly to the hydrogen-annealing step, and therefore provides similar adverse effects to the ferroelectric film.
FIG. 1 shows a typical configuration of an embedded LSI having a logic circuit section 16 and a FeRAM section 11 disposed as a FeRAM macro block, and FIG. 2 is a schematic sectional view of the LSI of FIG. 1. The FeRAM section 11 includes a FeRAM cell array 12 and a peripheral circuit 14 disposed in the periphery of the FeRAM section 11. The FeRAM cell array 12 is covered by a hydrogen barrier layer 18, which protects the FeRAM cell array 12 against the hydrogen generated during the hydrogen-annealing step conducted to the logic circuit section 16 and the peripheral circuit 14 of the FeRAM section 11. The term xe2x80x9chydrogen barrier layerxe2x80x9d as used herein means a film that prevents hydrogen from penetrating therethrough, such as a film made of a hydrogen-containing alloy or a metallic film having a barrier property against hydrogen.
The FeRAM cell array 12, the peripheral circuit 14 and the logic circuit section 16 are separated from one another by isolation films 19 constituting boundary areas, as shown in FIG. 2. Each FeRAM cell includes a MOSFET 36 having a pair of source/drain regions 22 and a gate electrode 20, and a ferroelectric capacitor 32 having a top electrode 26, a capacitor insulator film 28 and a bottom electrode 30. One of the source/drain regions 22 is connected to the top electrode 26 via a contact plug 33 and a first level interconnect 34.
The logic circuit section 16 includes a MOSFET 38, whereas the peripheral circuit 14 includes a MOSFET 36 having source/drain regions, one of which is connected to the bottom electrode 30 of the capacitor 32 via a contact plug 35 and a first level interconnect 34. Above the first level interconnects 34, second level interconnects 37 extend which are connected to the first level interconnects 34 and one of source/drain regions of the MOSFET 38.
The hydrogen barrier layer 18 disposed between the first level interconnects 34 and the second level interconnects 37 covers the FeRAM cell array 12 and extends to the boundary between the FeRAM cell array 12 and the peripheral circuit 14.
In the embedded LSI as described above, the capacitor insulator film 28 in the ferroelectric capacitor 32 is damaged by the hydrogen generated in the hydrogen-annealing process conducted for the logic circuit section 16 and the peripheral circuit 14. The hydrogen obliquely enters the periphery of the FeRAM cell array 12 beyond the edge of the hydrogen barrier layer 32.
It is proposed to provide a hydrogen barrier layer covering the entire area for the chip including the logic circuit section 16, FeRAM cell array a12 nd the peripheral circuit 14. However, in this case, MOSFETs 36 and 38 in the logic circuit section 16 and the peripheral circuit are not subjected to hydrogen-annealing, resulting in degradation of the transistor characteristics. The degradation of the transistor characteristics may incur malfunction of the logic circuit section 16 or reduction of the operational margin thereof.
It is therefore an object of the present invention to provide an embedded LSI including a FeRAM section having a ferroelectric capacitor in each memory cell and a logic circuit section having MOSFETs, the ferroelectric capacitor and the MOSFETs having excellent characteristics.
The present invention provides an embedded LSI including a substrate, a FeRAM section and a logic circuit section formed on the substrate for operating in association with each other, the FeRAM section including an array of FeRAM cells each including a ferroelectric capacitor and an associated peripheral circuit, a boundary area for separating the FeRAM section from the logic circuit section, a hydrogen barrier layer for covering substantially an entire area of the FeRAM section and exposing the logic circuit section, and an interconnect structure including first level interconnects and second level interconnects for connecting the FeRAM cell array, the peripheral circuit and the logic circuit section, the hydrogen barrier layer having an edge substantially aligned with the boundary area.
In accordance with the present invention, the hydrogen barrier layer covering the entire area of the FeRAM section including the FeRAM cell array and the peripheral area can effectively protect the ferroelectric capacitor during the hydrogen-annealing step which recovers the MOSFETs in the logic circuit section from the damages incurred by formation of the metallic interconnect structure.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.